BUDAPESTI MŰSZAKI ÉS GAZDASÁGTUDOMÁNYI EGYETEM VILLAMOSMÉRNÖKI ÉS INFORMATIKAI KAR MÉRÉSTECHNIKA ÉS INFORMÁCIÓS RENDSZEREK TANSZÉK Constraint-ek Fehér Béla Szántó Péter, Lazányi János, Raikovich Tamás BME MIT atórium
Attribútumok Szintézer direktívák Attributum készlet szintézer függő Signal/variable, példány, entity, entity test is port( ); attribute opt_mode: string; attribute opt_mode of test: entity is "area"; end test; architecture rtl of test is attribute max_fanout : string; signal res : std_logic_vector(7 downto 0); attribute max_fanout of res : signal is 50 ; begin end rtl;
FSM_EXTRACT Attribútumok (1.) attribute FSM_EXTRACT : string; attribute FSM_EXTRACT of state: signal is TRUE ; FSM_STYLE attribute FSM_STYLE : string; attribute FSM_STYLE of state: signal is lut ; FSM_ENCODING -- LUT, BRAM attribute FSM_ENCODING : string; attribute FSM_ENCODING of state: signal is one-hot ; -- auto, one-hot, compact, sequential, gray, johnson, user type state_type is (IDLE, CFG_RAM_RD, PREPARE, REQ, TRANSFER, SLAVE_TERM, CFG_RAM_WR); signal state : state_type; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "user"; attribute enum_encoding : string; attribute enum_encoding of state_type : type is "0000001 0000010 0000100 0001000 0010000 0100000 1000000";
FSM példa attribute fsm_encoding : string; attribute enum_encoding : string; type state_type is (RX_DW0DW1, RX_REQ_DW23_WR32, RX_REQ_DW23_WR64, RX_REQ_DW45_WR64, RX_REQ_DW23_RD32, RX_REQ_DW23_RD64, RX_CPLD_DW23_32, RX_CPLD_D32, RX_WAIT_CPL); attribute enum_encoding of state_type : type is "0000 0001 0010 0011 0100 0101 0110 0111 1000 "; signal rx_state : state_type; attribute fsm_encoding of rx_state : signal is "user"; Found finite state machine <FSM_0> for signal <rx_state>. -------------------------------------------------------- States 9 Transitions 25 Inputs 9 Outputs 10 Clock clk (rising_edge) Reset rst (positive) Reset type synchronous Reset State rx_dw0dw1 Power Up State rx_dw0dw1 Encoding user Implementation LUT -------------------------------------------------------- <rx_state[1:4]> with user encoding. ------------------------------ State Encoding ------------------------------ rx_dw0dw1 0000 rx_req_dw23_wr32 0001 rx_req_dw23_wr64 0010 rx_req_dw45_wr64 0011 rx_req_dw23_rd32 0100 rx_req_dw23_rd64 0101 rx_cpld_dw23_32 0110 rx_cpld_d32 0111 rx_wait_cpl 1000 ------------------------------
Attribútumok (2.) REGISTER_DUPLICATION attribute REGISTER_DUPLICATION : string; attribute REGISTER_DUPLICATION of test: entity is yes ; EQUIVALENT_REGISTER_REMOVAL attribute EQUIVALENT_REGISTER_REMOVAL : string; attribute EQUIVALENT_REGISTER_REMOVAL of test: entity is yes ; REGISTER_BALANCING attribute REGISTER_BALANCING : string; attribute REGISTER_BALANCING of test: entity is yes ; -- signal/entity; yes, no, forward, backward attribute MOVE_FIRST_STAGE : string; attribute MOVE_FIRST_STAGE of test: entity is yes ; attribute MOVE_LAST_STAGE : string; attribute MOVE_LAST_STAGE of test: entity is yes ;
Attribútumok (3.) USE_CLOCK_ENABLE attribute USE_CLOCK_ENABLE : string; attribute USE_CLOCK_ENABLE of data: signal is yes ; -- signal, entity, component, instance; auto, yes, no USE_SYNC_RESET attribute USE_SYNC_RESET : string; attribute USE_SYNC_RESET of test: entity is yes ; USE_SYNC_SET attribute USE_SYNC_SET : string; attribute USE_SYNC_SET of test: entity is yes ; Megj: setup time-ok: D: 0,27; CE: 0,47; RST: 0,78
Attribútumok (4.) MAX_FANOUT attribute MAX_FANOUT : string; attribute MAX_FANOUT of data: signal is 5 ; -- signal, entity; integer KEEP attribute KEEP : string; attribute KEEP of data: signal is TRUE ; IOB attribute IOB : string; attribute IOB of test: label is TRUE ; -- component, entity, label; auto, true, false
Attribútumok (5.) ROM_STYLE attribute ROM_STYLE : string; attribute ROM_STYLE of mem: signal is distributed ; -- signal, entity; auto, block, distributed --!! ROM_EXTRACT RAM_STYLE attribute RAM_STYLE : string; attribute RAM_STYLE of data: signal is block ; -- signal, entity; auto, block, distributed --!! RAM_EXTRACT SHREG_EXTRACT attribute SHREG_EXTRACT: string; attribute SHREG_EXTRACT of srl: signal is yes ;
Attribútumok (6.) USE_CARRY_CHAIN attribute USE_CARRY_CHAIN : string; attribute USE_CARRY_CHAIN of add: signal is no MULT_STYLE attribute MULT_STYLE : string; attribute MULT_STYLE of data: signal is block ; -- auto, block, pipe_block, lut, pipe_lut, kcm, csd USE_DSP48 attribute USE_DSP48 : string; attribute USE_DSP48 of data: signal is yes ;
Attribútumok (7.) OPT_MODE attribute OPT_MODE : string; attribute OPT_MODE of test: entity is area ; -- entity; area, speed Példa: PORTOK ); attribute opt_mode: string; attribute opt_mode of test: entity is "area"; end test;
RLOC attribute u_set : string; attribute u_set of XORCY_L_DW: label is ("SET" & str(num, 10)); attribute u_set of REG_OUT_DW: label is ("SET" & str(num, 10)); attribute rloc: string; attribute rloc of XORCY_L_DW : label is "X0Y0"; attribute rloc of REG_OUT_DW : label is "X0Y0"; muxcy_out(0) <= '0'; GEN_MUXCY: for I in 0 to DW generate mux_sel(i) <= (not op_a(i)) xor op_b(i); -- op_a!= op_b MUXCY_L_i : MUXCY_L port map ( LO => muxcy_out(i+1), CI => muxcy_out(i), DI => op_a(i), S => mux_sel(i) ); end generate; XORCY_L_DW: XORCY_L port map ( LO => sub_res(dw), CI => muxcy_out(dw+1), LI => mux_sel(dw) ); REG_OUT_DW: FDCE port map ( Q => res(dw), C => clk, CE => en, CLR => '0', D => sub_res(dw) );
I/O constraint-ek (UCF) LOC location constraint láb megadása IOSTANDARD Pl. LVCMOS, LVTTL, DIFF_SSTL_18_II PULLUP, PULLDOWN Gyenge fel-, lehúzó ellenállás Net DDR2_CS_n[1] LOC= B34 IOSTANDARD=SSTL18_II;
Időzítések (UCF) Csoportok INST *cpu_if* TNM=FFS TNM_CPU_REGS; INST *filter* TNM=FFS TNM_FILTER_REGS; -- FFS, RAMS, LATCHES, CPUS, MULTS Explicit TIMESPEC "TS_FALSE1" = FROM "TNM_CPUREGS" TO TNM_FILTER_REGS 10 ns; False Path TIMESPEC "TS_FALSE1" = FROM "TNM_CPUREGS" TO TNM_FILTER_REGS TIG; Clock-domain NET "clk1" TNM_NET = "clk1"; NET "clk2" TNM_NET = "clk2"; TIMESPEC TS_clk1_to_clk2 = FROM clk1 TO clk2 10 ns;
Elhelyezés Csoport AREA_GROUP "AGROUP1" RANGE = SLICE_X6Y11:SLICE_X9Y6 ; GROUP: CLOSED, OPEN PLACE: CLOSED, OPEN Elemek hozzárendelése INST "RAM_CCNT" AREA_GROUP = "AGROUP1";
Összefoglalás Az FPGA erőforrások használata a HDL nyelvekből különböző módokon is elérhető Érdemes a magasabb szintű leírást használni Kevesebb munka, tömör leírás Egyértelmű tervezői szándék specifikáció Eszköz független leírás, könnyebben migrálható más eszközökre A speciális funkciók, egyedi beállítások szükségessé tehetik az alacsonyszintű technológiai primitívek használatát