TL431A, B Series, NCV431A, B Series, SCV431A. Programmable Precision References

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1 TL43, B Series, NC43, B Series, SC43 Programmable Precision References The TL43, B integrated circuits are threeterminal programmable shunt regulator diodes. These monolithic IC voltage references operate as a low temperature coefficient zener which is programmable from ref to 36 with two external resistors. These devices exhibit a wide operating current range of. m to m with a typical dynamic impedance of.22. The characteristics of these references make them excellent replacements for zener diodes in many applications such as digital voltmeters, power supplies, and op amp circuitry. The 2.5 reference makes it convenient to obtain a stable reference from 5. logic supplies, and since the TL43, B operates as a shunt regulator, it can be used as either a positive or negative voltage reference. Features Programmable Output oltage to 36 oltage Reference Tolerance: ±.4%, 25 C (TL43B) Low Dynamic Output Impedance,.22 Typical Sink Current Capability of. m to m Equivalent FullRange Temperature Coefficient of 5 ppm/ C Typical Temperature Compensated for Operation over Full Rated Operating Temperature Range Low Output Noise oltage NC/SC Prefixes for utomotive and Other pplications Requiring Unique Site and Control Change Requirements; ECQ Qualified and PPP Capable These Devices are PbFree, Halogen Free/BFR Free and are RoHS Compliant Pin. Reference 2. node 3. Cathode Cathode 8 Reference N/C 2 7 N/C N/C N/C node N/C (Top iew) TO92 (TO226) LP SUFFIX CSE 29 PDIP8 P SUFFIX CSE 626 Micro8 DM SUFFIX CSE 846 SOIC8 D SUFFIX CSE 75 Cathode 8 Reference node 2 7 node 3 6 N/C 4 5 N/C (Top iew) This is an internally modified SOIC8 package. Pins 2, 3, 6 and 7 are electrically common to the die attach flag. This internal lead frame modification increases power dissipation capability when appropriately mounted on a printed circuit board. This modified package conforms to all external dimensions of the standard SOIC8 package. ORDERING INFORMTION See detailed ordering and shipping information on page 3 of this data sheet. DEICE MRKING INFORMTION See general marking information in the device marking section on page 4 of this data sheet. Semiconductor Components Industries, LLC, 25 January, 25 Rev. 37 Publication Order Number: TL43/D

2 TL43, B Series, NC43, B Series, SC43 Cathode (K) Cathode (K) Reference (R) node () Figure. Symbol Reference (R) pf Reference (R) + - Cathode (K) 3.28 k 2.4 k 7.2 k 2 pf 4. k 5 k 2.5 ref. k node () Figure 2. Representative Block Diagram This device contains 2 active transistors. node () Figure 3. Representative Schematic Diagram Component values are nominal MXIMUM RTINGS (Full operating ambient temperature range applies, unless otherwise noted.) Rating Symbol alue Unit Cathode to node oltage K 37 Cathode Current Range, Continuous I K to +5 m Reference Current Range, Continuous I ref.5 to + m Operating Junction Temperature T J 5 C Operating mbient Temperature Range T C TL43I, TL43I, TL43BI 4 to +85 TL43C, TL43C, TL43BC to +7 NC43I, NC43B, TL43B, SC43I 4 to +25 Storage Temperature Range T stg 65 to +5 C Total Power P D W Derate above 25 C mbient Temperature D, LP Suffix Plastic Package.7 P Suffix Plastic Package. DM Suffix Plastic Package.52 Total Power T C = 25 C P D W Derate above 25 C Case Temperature D, LP Suffix Plastic Package.5 P Suffix Plastic Package 3. ESD Rating (Note ) Human Body Model per JEDEC JESD224F Machine Model per JEDEC JESD225C Charged Device Model per JEDEC JESD22CE Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.. This device contains latchup protection and exceeds ± m per JEDEC standard JESD78. RECOMMENDED OPERTING CONDITIONS 8 HBM MM CDM >2 >2 >5 Condition Symbol Min Max Unit Cathode to node oltage K ref 36 Cathode Current I K. m Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 2

3 TL43, B Series, NC43, B Series, SC43 THERML CHRCTERISTICS Characteristic Symbol D, LP Suffix Package P Suffix Package DM Suffix Package Thermal Resistance, Junctiontombient R J C/W Thermal Resistance, JunctiontoCase R JC 83 4 C/W ELECTRICL CHRCTERISTICS (, unless otherwise noted.) Characteristic Reference oltage (Figure ) K = ref, I K = m T = T low to T high (Note ) Reference oltage Deviation Over Temperature Range (Figure, Notes, 2) K = ref, I K = m Ratio of Change in Reference oltage to Change in Cathode to node oltage I K = m (Figure 2), K = to ref K = 36 to Reference Current (Figure 2) I K = m, R = k, R2 = T = T low to T high (Note ) Reference Current Deviation Over Temperature Range (Figure 2, Note, 4) I K = m, R = k, R2 = Minimum Cathode Current For Regulation K = ref (Figure ) OffState Cathode Current (Figure 3) K = 36, ref = Dynamic Impedance (Figure, Note 3) K = ref, I K =. m to m f. khz Symbol ref TL43I TL43C Min Typ Max Min Typ Max Unit Unit ref m ref K I ref m/ I ref I min m I off 2 2 n Z K Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. T low = 4 C for TL43IP TL43ILP, TL43IP, TL43ILP, TL43BID, TL43BIP, TL43BILP, TL43IDM, TL43IDM, TL43BIDM; = C for TL43CP, TL43CLP, TL43CP, TL43CLP, TL43CD, TL43CD, TL43BCD, TL43BCP, TL43BCLP, TL43CDM, TL43CDM, TL43BCDM T high = +85 C for TL43IP, TL43ILP, TL43IP, TL43ILP, TL43BID, TL43BIP, TL43BILP, TL43IDM, TL43IDM, TL43BIDM = +7 C for TL43CP, TL43CLP, TL43CP, TL43CD, TL43BCD, TL43BCP, TL43BCLP, TL43CDM, TL43CDM, TL43BCDM 3. The deviation parameter ref is defined as the difference between the maximum and minimum values obtained over the full operating ambient temperature range that applies. ref max ref min D ref = ref max - ref min T = T 2 - T T mbient Temperature The average temperature coefficient of the reference input voltage, ref is defined as: T2 ref X ppm 6 x 6 ref ref C T T ref ref can be positive or negative depending on whether ref Min or ref Max occurs at the lower ambient temperature. (Refer to Figure 6.) Example : 8. m and slope is positive, ref.8 x 2.495, T 7C ref 45.8 ppmc ref 7 (2.495) 4. The dynamic impedance Z K is defined as: Z K K I K. When the device is programmed with two external resistors, R and R2, (refer to Figure 2) the total dynamic impedance of the circuit is defined as: Z K Z K R R2 3

4 TL43, B Series, NC43, B Series, SC43 ELECTRICL CHRCTERISTICS (, unless otherwise noted.) Characteristic Reference oltage (Figure ) K = ref, I K = m T = T low to T high Symbol ref TL43I / NC43I/ SC43I TL43C TL43BC / TL43BI / TL43B / NC43B Min Typ Max Min Typ Max Min Typ Max Unit Reference oltage Deviation Over Temperature Range (Figure, Notes 5, 6) K = ref, I K = m ref m Ratio of Change in Reference oltage to Change in Cathode to node oltage I K = m (Figure 2), K = to ref K = 36 to Reference Current (Figure 2) I K = m, R = k, R2 = T = T low to T high (Note 5) Reference Current Deviation Over Temperature Range (Figure 2, Note 5) I K = m, R = k, R2 = Minimum Cathode Current For Regulation K = ref (Figure ) OffState Cathode Current (Figure 3) K = 36, ref = Dynamic Impedance (Figure, Note 7) K = ref, I K =. m to m f. khz ref K I ref I ref m/ I min m I off n Z K Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. T low = 4 C for TL43IP TL43ILP, TL43IP, TL43ILP, TL43BID, TL43BIP, TL43BILP, TL43B, TL43IDM, TL43IDM, TL43BIDM, NC43IDMR2G, NC43IDR2G, NC43BDR2G, SC43IDMR2G = C for TL43CP, TL43CLP, TL43CP, TL43CLP, TL43CD, TL43CD, TL43BCD, TL43BCP, TL43BCLP, TL43CDM, TL43CDM, TL43BCDM, SC43IDMR2G T high = +85 C for TL43IP, TL43ILP, TL43IP, TL43ILP, TL43BID, TL43BIP, TL43BILP, TL43IDM, TL43IDM, TL43BIDM = +7 C for TL43CP, TL43CLP, TL43CP, TL43CD, TL43BCD, TL43BCP, TL43BCLP, TL43CDM, TL43CDM, TL43BCDM = +25 C TL43B, NC43IDMR2G, NC43IDR2G, NC43BDMR2G, NC43BDR2G, SC43IDMR2G 6. The deviation parameter ref is defined as the difference between the maximum and minimum values obtained over the full operating ambient temperature range that applies. ref max ref min ref = ref max - ref min T = T 2 - T T T2 mbient Temperature The average temperature coefficient of the reference input voltage, ref is defined as: ref X ppm 6 x 6 ref ref C T T ref ref can be positive or negative depending on whether ref Min or ref Max occurs at the lower ambient temperature. (Refer to Figure 6.) Example : 8. m and slope is positive, ref.8 x 2.495, T 7C ref 45.8 ppmc ref 7 (2.495) 7. The dynamic impedance Z K is defined as Z K K I K When the device is programmed with two external resistors, R and R2, (refer to Figure 2) the total dynamic impedance of the circuit is defined as: Z K Z K R R2 8. NC43IDMR2G, NC43IDR2G, NC43BDMR2G, NC43BDR2G, SC43IDMR2G T low = 4 C, T high = +25 C. Guaranteed by design. NC prefix is for automotive and other applications requiring unique site and control change requirements. 4

5 TL43, B Series, NC43, B Series, SC43 I K K R I ref I K K I off K ref R2 K ref R R2 I ref R Figure. Test Circuit for K = ref ref Figure 2. Test Circuit for K > ref Figure 3. Test Circuit for I off I K, CTHODE CURRENT (m) K = ref K I K IK, CTHODE CURRENT ( μ ) K = ref I K K I Min K, CTHODE OLTGE () Figure 4. Cathode Current versus Cathode oltage K, CTHODE OLTGE () Figure 5. Cathode Current versus Cathode oltage ref, REFERENCE INPUT OLTGE (m) ref K I K K = ref I K = m 25 5 ref Max = 255 m ref Typ = 2495 m ref Min = 244 m Iref, REFERENCE INPUT CURRENT ( μ ) k I K = m K I ref I K T, MBIENT TEMPERTURE ( C) T, MBIENT TEMPERTURE ( C) Figure 6. Reference oltage versus mbient Temperature Figure 7. Reference Current versus mbient Temperature 5

6 TL43, B Series, NC43, B Series, SC43 Δ ref, REFERENCE INPUT OLTGE (m) K I. R K -24 R2 ref K, CTHODE OLTGE () 3 I K = m Figure 8. Change in Reference oltage versus Cathode oltage 4 Ioff, OFF-STTE CTHODE CURRENT (n). k T, MBIENT TEMPERTURE (5C) K = 36 ref = K I off Figure 9. OffState Cathode Current versus mbient Temperature ZK, DYNMIC IMPEDNCE ( Ω ).. k Output I K GND I K =. m to m ZK, DYNMIC IMPEDNCE ( Ω ) K = ref I K =. m to m f. khz.k Output I K GND.. k k k. M M f, FREQUENCY (MHz) T, MBIENT TEMPERTURE ( C) Figure. Dynamic Impedance versus Frequency Figure. Dynamic Impedance versus mbient Temperature, OPEN LOOP OLTGE GIN (db) OL I K = m -. k k 9. F k I 5k K 8.25k. M Output 23 GND M NOISE OLTGE (n/ Hz) K = ref I K = m. k k I K Output k f, FREQUENCY (MHz) f, FREQUENCY (Hz) Figure 2. OpenLoop oltage Gain versus Frequency Figure 3. Spectral Noise Density 6

7 TL43, B Series, NC43, B Series, SC43 OLTGE SWING () Output Monitor Pulse Generator f = khz 22 Output 5 GND IK, CTHODE CURRENT (m) Unstable rea B C D Programmed K () ref 5. 5 Stable B D C B Stable t, TIME (s). nf nf nf. F F F C L, LOD CPCITNCE Figure 4. Pulse Response Figure 5. Stability Boundary Conditions 5 5 I K I K k + C L + C L Figure 6. Test Circuit For Curve of Stability Boundary Conditions Figure 7. Test Circuit For Curves B, C, nd D of Stability Boundary Conditions TYPICL PPLICTIONS + out R + out R R2 out R R2 ref Figure 8. Shunt Regulator out R R2 ref Figure 9. High Current Shunt Regulator R2 7

8 TL43, B Series, NC43, B Series, SC43 MC785 + In Out out Common R + out R out R R2 ref 5. out(min) ref R2 Figure 2. Output Control for a ThreeTerminal Fixed Regulator out R R2 ref in(min) out be out(min) ref R2 Figure 2. Series Pass Regulator + R CL I out + I sink I out ref R CL R S I Sink ref R S Figure 22. Constant Current Source Figure 23. Constant Current Sink + out R + R out R2 out(trip) R R2 ref Figure 24. TRIC Crowbar R2 out(trip) R R2 ref Figure 25. SRC Crowbar 8

9 TL43, B Series, NC43, B Series, SC43 + out l R R3 + out R2 R4 in L.E.D. indicator is `on' when + is between the upper and lower limits. LowerLimit R R2 ref UpperLimit R3 R4 ref Figure 26. oltage Monitor th = ref in out < ref + > ref 2. Figure 27. SingleSupply Comparator with TemperatureCompensated Threshold N m T l = 33 to k 5 k % % k. k 5 k % R X k 5. M % Range. M 25 - LM + R x out Range k Calibrate -5. out 8. * Thermalloy * THM 624 * Heatsink on * LP Package * T I 36 k. F 47 F.5 F Tone 56 k k 25 k + olume 47 k Figure 28. Linear Ohmmeter Figure 29. Simple 4 mw Phono mplifier 9

10 TL43, B Series, NC43, B Series, SC43 in = to 2. k TIP5 4.7 k 4.7 k 5 2. N5823 out = 5. I out = F 4.7 k MPS2.F k 47 F +. F 2.2 k 5 k Figure 3. High Efficiency StepDown Switching Converter Test Conditions Results Line Regulation in = to 2, I o =. 53 m (.%) Load Regulation in = 5, I o = to. 25 m (.5%) Output Ripple in =, I o =. 5 mpp P..R.D. Output Ripple in = 2, I o =. mpp P..R.D. Efficiency in = 5, I o =. 82%

11 TL43, B Series, NC43, B Series, SC43 PPLICTIONS INFORMTION The TL43 is a programmable precision reference which is used in a variety of ways. It serves as a reference voltage in circuits where a nonstandard reference voltage is needed. Other uses include feedback control for driving an optocoupler in power supplies, voltage monitor, constant current source, constant current sink and series pass regulator. In each of these applications, it is critical to maintain stability of the device at various operating currents and load capacitances. In some cases the circuit designer can estimate the stabilization capacitance from the stability boundary conditions curve provided in Figure 5. However, these typical curves only provide stability information at specific cathode voltages and at a specific load condition. dditional information is needed to determine the capacitance needed to optimize phase margin or allow for process variation. simplified model of the TL43 is shown in Figure 3. When tested for stability boundaries, the load resistance is 5. The model reference input consists of an input transistor and a dc emitter resistance connected to the device anode. dependent current source, Gm, develops a current whose amplitude is determined by the difference between the.78 internal reference voltage source and the input transistor emitter voltage. portion of Gm flows through compensation capacitance, C P2. The voltage across C P2 drives the output dependent current source, Go, which is connected across the device cathode and anode. Model component values are: ref =.78 Gm = exp (I C /26 m) where I C is the device cathode current and Gm is in mhos Go =.25 ( cp 2) mhos. Resistor and capacitor typical values are shown on the model. Process tolerances are ± 2% for resistors, ±% for capacitors, and ±4% for transconductances. n examination of the device model reveals the location of circuit poles and zeroes: P 7.96 khz 2 R C 2 *. M * 2 pf GM P P2 Z 6 khz 2 R C 2 * M *.265 pf P2 P2 5 khz 2 R C 2 *5.9k*2pF Z P In addition, there is an external circuit pole defined by the load: P L 2 R C L L lso, the transfer dc voltage gain of the TL43 is: Example : G G M R GM GoR L I C m, R L 23,C L. Define the transfer gain. The DC gain is: G G M R GM GoR L (2.38)(. M)(.25 )(23) db Loop gain G 8.25 k db 8.25 k 5 k The resulting transfer function Bode plot is shown in Figure 32. The asymptotic plot may be expressed as the following equation: jf 5 khz v 65 jf jf 8. khz 6 khz The Bode plot shows a unity gain crossover frequency of approximately 6 khz. The phase margin, calculated from the equation, would be 55.9 degrees. This model matches the OpenLoop Bode Plot of Figure 2. The total loop would have a unity gain frequency of about 3 khz with a phase margin of about 44 degrees.

12 TL43, B Series, NC43, B Series, SC43 CC R L C L 5 k 9. F 3 Cathode 8.25 k Ref 5 k ref R ref 6 G M R GM. M C P 2 pf R P2 M R Z 5.9 k Go. mho C P2.265 pf node 2 Figure 3. Simplified TL43 Device Model v, OPEN-LOOP OLTGE GIN (db) TL43 OPEN-LOOP OLTGE GIN ERSUS FREQUENCY f, FREQUENCY (Hz) Figure 32. Example Circuit Open Loop Gain Plot Example 2. I C = 7.5 m, R L = 2.2 k, C L =. F. Cathode tied to reference input pin. n examination of the data sheet stability boundary curve (Figure 5) shows that this value of load capacitance and cathode current is on the boundary. Define the transfer gain. The DC gain is: G G M R GM GoR L (2.323)(. M)(.25 )(22) db The resulting open loop Bode plot is shown in Figure 33. The asymptotic plot may be expressed as the following equation: jf 5 khz v 65 jf jf jf 8. khz 6 khz 7.2 khz Note that the transfer function now has an extra pole formed by the load capacitance and load resistance. Note that the crossover frequency in this case is about 25 khz, having a phase margin of about 46 degrees. Therefore, instability of this circuit is likely. v, OPEN-LOOP GIN (db) TL43 OPEN-LOOP BODE PLOT WITH LOD CP f, FREQUENCY (Hz) Figure 33. Example 2 Circuit Open Loop Gain Plot With three poles, this system is unstable. The only hope for stabilizing this circuit is to add a zero. However, that can only be done by adding a series resistance to the output capacitance, which will reduce its effectiveness as a noise filter. Therefore, practically, in reference voltage applications, the best solution appears to be to use a smaller value of capacitance in low noise applications or a very large value to provide noise filtering and a dominant pole rolloff of the system. 2

13 TL43, B Series, NC43, B Series, SC43 ORDERING INFORMTION Device Marking Code Operating Temperature Range Package Code Shipping Information Tolerance TL43CDG C.% TL43BCDG BC 98 Units / Rail.4% TL43CDG C SOIC8 2.2% TL43CDR2G C (PbFree).% TL43BCDR2G BC 25 / Tape & Reel.4% TL43CDR2G C 2.2% TL43CDMR2G TC.% TL43BCDMR2G TBC Micro8 (PbFree) 4 / Tape & Reel.4% TL43CDMR2G TC 2.2% TL43CPG CP.% TL43BCPG BCP PDIP8 (PbFree) 5 Units / Rail.4% TL43CPG CP 2.2% TL43CLPG CLP C to 7 C.% TL43BCLPG BCLP 2 Units / Bag.4% TL43CLPG CLP 2.2% TL43CLPRG CLP.% TL43BCLPRG BCLP.4% TL43CLPRG CLP 2.2% TO92 2 / Tape & Reel TL43CLPREG CLP.% (PbFree) TL43BCLPREG BCLP.4% TL43CLPREG CLP 2.2% TL43CLPRPG CLP 2 / Tape & mmo Box.% TL43BCLPRMG BCLP.4% TL43CLPRMG CLP 2 / FanFold TL43CLPRPG CLP 2.2% TL43IDG I.% TL43BIDG BI 98 Units / Rail.4% TL43IDG I SOIC8 2.2% TL43IDR2G I (PbFree).% TL43BIDR2G BI 25s / Tape & Reel.4% TL43IDR2G I 2.2% TL43IDMR2G TI.% TL43BIDMR2G TBI Micro8 (PbFree) 4 / Tape & Reel.4% TL43IDMR2G TI 2.2% TL43IPG IP.% PDIP8 TL43BIPG BIP 5 Units / Rail.4% 4 C to 85 C (PbFree) TL43IPG IP 2.2% TL43ILPG ILP.% TL43BILPG BILP 2 Units / Bag.4% TL43ILPG ILP 2.2% TL43ILPRG ILP.% TL43BILPRG BILP TO92.4% 2 / Tape & Reel SC43ILPRG ILP (PbFree) 2.2% TL43ILPRG ILP TL43ILPRMG ILP TL43ILPRPG 2 / Tape & mmo Box.% TL43ILPRPG ILP 2.2% For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8/D. *NC/SC Prefixes for utomotive and Other pplications Requiring Unique Site and Control Change Requirements; ECQ Qualified and PPP Capable. 3

14 TL43, B Series, NC43, B Series, SC43 ORDERING INFORMTION Device TL43BDG TL43BDR2G TL43BDMR2G Marking Code B TB Operating Temperature Range Package Code SOIC8 (PbFree) Micro8 (PbFree) TL43BLPG TO92 BLP TL43BLPRG (PbFree) TL43BPG PDIP8 BP (PbFree) 4 C to 25 C NC43IDMR2G* RN Micro8 SC43IDMR2G* RP (PbFree) NC43IDR2G* SOIC8 (PbFree) NC43BDMR2G* Micro8 NB (PbFree) NC43BDR2G* SOIC8 B (PbFree) Shipping Information 98 Units / Rail 25 / Tape & Reel 4 / Tape & Reel 2 Units / Bag 2 / Tape & Reel Tolerance.4% 5 Units / Rail.4% 4 / Tape & Reel 25 / Tape & Reel 4 / Tape & Reel 25 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8/D. *NC/SC Prefixes for utomotive and Other pplications Requiring Unique Site and Control Change Requirements; ECQ Qualified and PPP Capable. %.4% MRKING DIGRMS SOIC8 D SUFFIX CSE 75 Micro8 CSE 846 PDIP8 CSE 626 TO92 (TO226) CSE xx LYW 8 xxx YW 8 TL43xxx WL YYWWG TL43 xxxx YWW 8 TL43 LYWx (Exception for the TL43CD and TL43ID only) xxxx = See Specific Marking Code = ssembly Location Y, YY = Year WW, W = Work Week or G = PbFree Package (Note: Microdot may be in either location) 4

15 TL43, B Series, NC43, B Series, SC43 PCKGE DIMENSIONS TO92 (TO226) CSE 29 ISSUE M STRIGHT LED BENT LED BULK PCK TPE & REEL MMO PCK R N B STRIGHT LED BULK PCK NOTES:. DIMENSIONING ND TOLERNCING PER NSI Y4.5M, CONTROLLING DIMENSION: INCH. 3. CONTOUR OF PCKGE BEYOND DIMENSION R IS UNCONTROLLED. 4. LED DIMENSION IS UNCONTROLLED IN P ND BEYOND DIMENSION K MINIMUM. P L SETING INCHES MILLIMETERS PLNE K DIM MIN MX MIN MX B C D X X D G H G J H J K C L N P SECTION XX R N R B BENT LED TPE & REEL MMO PCK NOTES:. DIMENSIONING ND TOLERNCING PER SME Y4.5M, CONTROLLING DIMENSION: MILLIMETERS. 3. CONTOUR OF PCKGE BEYOND DIMENSION R IS UNCONTROLLED. 4. LED DIMENSION IS UNCONTROLLED IN P ND BEYOND DIMENSION K MINIMUM. P T MILLIMETERS SETING PLNE K DIM MIN MX B C D.4.54 G X X D G J.39.5 K J N P.5 4. C R SECTION XX N 5

16 TL43, B Series, NC43, B Series, SC43 PCKGE DIMENSIONS PDIP8 CSE 6265 ISSUE N NOTE 8 D D b2 TOP IEW e/2 e SIDE IEW E B 2 NOTE 3 L C SETING PLNE H eb 8X b END IEW. M C M B M NOTE 6 E c END IEW WITH LEDS CONSTRINED M NOTE 5 NOTES:. DIMENSIONING ND TOLERNCING PER SME Y4.5M, CONTROLLING DIMENSION: INCHES. 3. DIMENSIONS, ND L RE MESURED WITH THE PCK- GE SETED IN JEDEC SETING PLNE GUGE GS3. 4. DIMENSIONS D, D ND E DO NOT INCLUDE MOLD FLSH OR PROTRUSIONS. MOLD FLSH OR PROTRUSIONS RE NOT TO EXCEED. INCH. 5. DIMENSION E IS MESURED T POINT.5 BELOW DTUM PLNE H WITH THE LEDS CONSTRINED PERPENDICULR TO DTUM C. 6. DIMENSION E3 IS MESURED T THE LED TIPS WITH THE LEDS UNCONSTRINED. 7. DTUM PLNE H IS COINCIDENT WITH THE BOTTOM OF THE LEDS, WHERE THE LEDS EXIT THE BODY. 8. PCKGE CONTOUR IS OPTIONL (ROUNDED OR SQURE CORNERS). INCHES MILLIMETERS DIM MIN MX MIN MX b b2.6 TYP.52 TYP C D D.5.3 E E e. BSC 2.54 BSC eb L M 6

17 TL43, B Series, NC43, B Series, SC43 PCKGE DIMENSIONS Micro8 CSE 8462 ISSUE J H E D E NOTES:. DIMENSIONING ND TOLERNCING PER NSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION DOES NOT INCLUDE MOLD FLSH, PROTRUSIONS OR GTE BURRS. MOLD FLSH, PROTRUSIONS OR GTE BURRS SHLL NOT EXCEED.5 (.6) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLED FLSH OR PROTRUSION. INTERLED FLSH OR PROTRUSION SHLL NOT EXCEED.25 (.) PER SIDE OBSOLETE, NEW STNDRD PIN ID T SETING PLNE.38 (.5) e b 8 PL.8 (.3) M T B S S MILLIMETERS INCHES DIM MIN NOM MX MIN NOM MX b c D E e.65 BSC.26 BSC L H E c L RECOMMENDED SOLDERING FOOTPRINT* 8X.48 8X PITCH DIMENSION: MILLIMETERS *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 7

18 TL43, B Series, NC43, B Series, SC43 PCKGE DIMENSIONS SOIC8 D SUFFIX CSE 757 ISSUE K X B Y Z H 8 G D 5 4 S C.25 (.) M Z Y S X S.25 (.) M SETING PLNE Y. (.4) M N X 45 M K J NOTES:. DIMENSIONING ND TOLERNCING PER NSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION ND B DO NOT INCLUDE MOLD PROTRUSION. 4. MXIMUM MOLD PROTRUSION.5 (.6) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DMBR PROTRUSION. LLOWBLE DMBR PROTRUSION SHLL BE.27 (.5) TOTL IN EXCESS OF THE D DIMENSION T MXIMUM MTERIL CONDITION THRU 756 RE OBSOLETE. NEW STNDRD IS 757. MILLIMETERS INCHES DIM MIN MX MIN MX B C D G.27 BSC.5 BSC H J K M 8 8 N S SOLDERING FOOTPRINT* SCLE 6: *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. mm inches Micro8 is a trademark of International Rectifier. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of SCILLC s product/patent coverage may be accessed at /site/pdf/patentmarking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICTION ORDERING INFORMTION LITERTURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 827 US Phone: or Toll Free US/Canada Fax: or Toll Free US/Canada orderlit@onsemi.com N. merican Technical Support: Toll Free US/Canada Europe, Middle East and frica Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative TL43/D